PRODUCT DESCRIPTION

The AZS10 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth. For a design that includes gain in the signal path, refer to the AZS15.

The AZS10 is a configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. Configurations options provide designers with a single IC buffer & translator solution that is extremely compact, flexible and high performance.

FEATURES

  • Configurable LVPECL or LVDS outputs
  • Optimized for ultra low phase noise (-167dBc/Hz, -165dBc/Hz)
  • Greater than 1GHz bandwidth
  • Selectable ÷1, ÷2 output
  • Selectable Enable logic
  • 2.375V to 3.6V operation

APPLICATION

  • PECL, LVDS clock reference & driver
  • PECL, LVDS signal conversion
  • Converting crystal or SAW based oscillators to LVPECL or LVDS output

ORDER NUMBERS

Order Number Package
AZS10XR Die
AZS10QG SON8
AZS10XW MSOP8
Description:

Ultra Low Phase Noise LVPECL, LVDS Buffer & Divider

Input:

Sine or CMOS

Output:

LVPECL

LVDS

Phase Noise:

-167dBc/Hz

Jitter:

26 fs

Bandwidth:

> 1.0GHz

Divider:

Selectable ÷1, ÷2

Enable:

Selectable Polarity

Supply Voltage:

2.5V to 3.3V

Packages:

Die

SON8

MSOP8