PRODUCT DESCRIPTION

The AZ100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Qb High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple AZ100LVEL33’s in a system.

FEATURES

  • > 5.0 GHz Toggle Frequency
  • 470ps Propagation Delay
  • 3V to 5.5V Power Supply
  • Internal Input Pulldown Resistors

APPLICATION

  • General applications

ORDER NUMBERS

Order Number Package
AZ100LVEL33NG MLP8
AZ100LVEL33DG SOIC8
AZ100LVEL33TG MSOP8
Description:

LVPECL ÷4 Divider

Input:

LVPECL

Output:

LVPECL

Phase Noise:

n/a

Jitter:

n/a

Bandwidth:

> 5.0 GHz

Divider:

Fixed ÷4

Enable:

n/a

Supply Voltage:

3.3V to 5.0V

Packages:

MLP8
MSOP8
SOIC8