| Part Number | Description / Function | Input Level | Output Level | Phase Noise | Bandwidth | Divider | Enable | Supply Voltage | Packages |
| AZ100LVEL32 | LVPECL ÷2 Divider | LVPECL | LVPECL | > 3.0 GHz | Fixed ÷2 | n/a | 3.0V to 5.5V | MLP8 | |
| AZ100LVEL33 | LVPECL ÷4 Divider | LVPECL | LVPECL | > 5.0 GHz | Fixed ÷4 | n/a | 3.0V to 5.5V | MLP8 | |
| AZP51 | Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider | Sine or CMOS | LVPECL | -165dBc/Hz | > 800MHz | Fixed ÷1 | Active HIGH | 3.0V to 3.6V | SC70-6 |
| AZP52 | Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider | Sine or CMOS | LVPECL | -165dBc/Hz | > 800MHz | Fixed ÷2 | Active HIGH | 3.0V to 3.6V | SC70-6 |
| AZP53 | Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider | Sine or CMOS | LVPECL | -165dBc/Hz | > 800MHz | Selectable ÷1, ÷2 | Selectable Polarity | 3.0V to 3.6V | Die QFN8 |
| AZP54 | Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider | Sine or CMOS | LVPECL | -165dBc/Hz | > 800MHz | Fixed ÷1 | Active LOW | 3.0V to 3.6V | SOT23-6 |
| AZP63 | Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider | Sine or CMOS | LVPECL | -165dBc/Hz | > 1.0GHz (÷1) | Selectable ÷1, ÷2 | Selectable Polarity | 3.0V to 3.6V | Die SON8 |
| AZP92 | LVPECL ÷1, ÷2 Clock Generator w/ Selectable Enable | LVPECL | LVPECL | -145dBc/Hz (÷1) | > 1.5GHz (÷1) | Selectable ÷1, ÷2 | Selectable Polarity & Threshold | 3.0V to 5.5V | MLP8 |
| AZP94 | LVPECL ÷1, ÷2 Clock Generator w/ Tri-State Compatible Outputs | LVPECL | LVPECL | -145dBc/Hz (÷1) | > 1.5GHz (÷1) | Selectable ÷1, ÷2 | Selectable Polarity & Threshold | 3.0V to 5.5V | MLP8 |
