The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate design of the AZ100ELT23 makes it ideal for applications that require the translation of a clock and a data signal. The AZ100ELT23 is a direct replacement for the ON Semi MC100ELT23.

Recommended for new designs

Block Diagram

  • • 3.5ns propagation delay
  • • <500ps output to output skew
  • • Differential PECL inputs
  • • CMOS/TTL outputs
  • • 5V analog supply
  • • Industrial Temp Range: -40°C to 85°C
  • • LVPECL to LVCMOS/LVTTL translation
  • • PECL to CMOS/TTL translation

Order Numbers

Part NumberPackageDimensionsQuantityMSL Rating
AZ100ELT23DGR1SOIC8.189/1.96in x .150/.157in10001
AZ100ELT23TGR1MSOP80.12in x 0.12in10001